(1) Field of the Invention
The present invention generally relates to a transmission circuit for transmitting fixed-length data such as cell data, and more particularly to a transmission circuit, for transmitting fixed-length data, in which the number of circuit elements can be decreased.
(2) Description of Related Art
Recently, to more effectively use a communication line, a system has been proposed in which information is divided into units each having a predetermined data length and being transmitted through the communication line. It is desired that a transmission circuit used in this system be of a small scale and that operations thereof be performed with a small power dissipation.
A unit referred to as a "cell" has been proposed. Two types of cells are used for transmitting desired information through the communication line. A first type of a cell is referred to, for example, as a normal cell and is constituted as shown in FIG. 1A. Referred to FIG. 1A, the normal cell is formed of a heading data (H), a head error correcting code (HEC) and an information field (F). The heading data includes destination data indicating a destination to which data should be transmitted. The head error correcting code (HEC) is used for correcting an error in the heading the data (H). The information field (F) is data, which is desired to be transmitted to the destination. A second type of a cell is referred to, for example, as an idle cell. The idle cell is transmitted through the communication line when there is no normal cell to be transmitted, That is, an idle cell includes no valid data and is used for filling idle time slots in the communication line. The idle cell is constituted as shown in FIG. 1B. Referring to FIG. 1B, the idle cell is also formed of a heading data (H), a head error correcting code (HEC) and an information field (F). The heading data (H) and the head error correcting code (HEC) of the idle cell have a fixed pattern. The information field of the idle cell has either a predetermined pattern or any pattern.
A conventional transmission circuit for transmitting cell data described above in ATM (Asynchronous Transfer Mode) is shown in FIG. 2.
Referring to FIG. 2, a cell data output unit 1 generates normal cells as shown in FIG. 1A and outputs them. An idle cell generating unit 12 generates idle cells as shown in FIG. 1B and outputs them. The cell data output unit 1 and the idle cell generating unit 12 are connected to a first selector 21. The first selector 21 has two input ports and one output port. A scrambler 3 scrambles the information field (F) of each of cells output from the first selector 21. The output port of the first selector 21 and the scrambler 3 are connected to a second selector 22. The second selector 22 has two input ports and one output port. An error correcting code generator 2 calculates an error correcting code based on the heading data in each normal cell. The output port of the second selector 22 and the error correcting code generator 2 are connected to a third selector 23. The third selector 23 has two input ports and one output port. A controller 65 controls the cell data output unit 1, the idle cell generating unit 12, the scrambler 3, the error correcting code generator 2 and the first, second and third selectors 21, 22 and 23. 8-bit parallel data is processed in this transmission circuit.
In the above conventional transmission circuit, three selectors 21, 22 and 23, each having two input ports and one output port, are provided. Each of the selectors 21, 22 and 23 has a circuit as shown in FIG. 3. The circuit shown in FIG. 3 corresponds to each bit in the 8-bit parallel data and is formed of three NAND gates and a D-type flip flop. Thus, each selector to which 8-bit data is supplied has eight circuits, shown in FIG. 3, arranged in parallel to each other.
The transmission circuit shown in FIGS. 2 and 3 operates in the following manner.
In a case where the normal cell is transmitted, first, the first selector 21 selects the cell data output unit 1, then the second selector 22 selects the output port of the first selector 21, and the third selector 21 selects the output port of the second selector 22. As a result, the heading data (H) of the normal cell output from the cell data output unit 1 passes through the first, second and third selectors 21, 22 and 23 and is output from this transmission circuit as it is. Next, the third selector 23 switches the selection to the error correcting code generator 2. The heading data (H) is supplied from the cell data output unit 1 to the error correcting code generator 2 via the first and second selectors 21 and 22. The error correcting code generator 2 calculates a head error correcting code (HEC). Then the head error correcting code (HEC) is output from the transmission circuit via the third selector 23 so as to be added to the heading data (H).
Then, the second selector 22 switches the selection to the scrambler 3 and the third selector 23 switches the selection to the output of the second selector 21. In this case, the information field (F) of the normal cell output from the cell data output unit 1 is supplied to the scrambler 3 via the first selector. The scrambler 3 scrambles the information field (F) of the normal cell so as to randomize bits in the information field (F). The information field (F) processed by the scrambler 3 is output from the transmission circuit via the second and third selectors 22 and 23. In this case, as the heading data (H) and the head error correcting code (HEC) are used for synchronizing operation of the normal cell, the heading data (H) and the head error correcting code (HEC) are not processed by the scrambler 3.
When there is no normal call to be transmitted, the idle cell is output from the transmission circuit so as to fill an idle time slot in the communication line. In this case, first, the first selector 21 selects the idle cell generating unit 12, the second selector 22 selects the output of the first selector 21, and the third selector 23 selects the output of the second selector 22. Under this condition, the heading data (H) and the head error correcting code (HEC) having predetermined bit patterns are output from the idle cell generating unit 12 and pass through the first, second and third selectors 21, 22 and 23. As a result, the heading data (H) and the head error correcting code (HEC) of the idle cell is output from the transmission circuit. Next, the second selector 22 switches the selection to the scrambler 3. The information field (F) of the idle cell is supplied from the idle cell generating unit 12 to the scrambler 3 via the first selector 21, so that the information field (F) is scrambled by the scrambler 3. As a result, the information field (F) of the idle cell processed by scrambler 3 is output from the transmission circuit via the second and third selectors 22 and 23.
According to the above processes, the normal cell as shown in FIG. 1A and the idle cell as shown in FIG. 1B are transmitted from the transmission circuit through the communication line. The above selecting operations of the first, second and third selectors 21, 22 and 23 are controlled by the controller 65.
The conventional transmission circuit for transmitting data cell by cell as described above must be provided with three selectors each having two input ports and one output port. Thus, in a case where 8-bit data is processed in the transmission circuit, the total numbers of NAND gates and D-type flip flops used in three selectors are respectively seventy two and twenty four. That is, a large number of circuit elements are needed in the conventional transmission circuit. Thus, the dissipation power of the transmission circuit increases.